1. Field of the Invention
The present invention relates to a clock switching circuit for switching between two sorts of clock signals.
2. Description of the Background Art
The Japanese patent laid-open publication No. 242529/1999 discloses an example of the conventional clock controller. FIG. 2 of this publication shows the clock controller aiming to switch between two clocks received on the respective two clock input terminals in response to an asynchronous clock switching signal supplied on a clock selection terminal, within a short time, such as not to cause a hazard.
FIG. 4 shows a clock controller which is also disclosed in the above Japanese publication, and includes a selector 4 for switching between the two input clocks #0 and #1, and a first selector controller 5 for controlling the selector 4. The clock controller also includes a first delay circuit 6 for delaying the clock switching signal and for routing the delayed signal to the first selector controller 5, and a signal holding circuit 7 for holding the clock selected by the selector 4 in response to the clock switching signal. The clock controller further includes another selector 8 for switching between the signal output from the signal holding circuit 7 and the signal output from the selector 4, and a second selector controller 9 for controlling the other selector 8. It also includes a second delay circuit 10 for delaying the clock switching signal and for routing the delayed signal to the second selector controller 9, and a counter 11 for generating a signal synchronized with the clock output from the selector 4 to route the so generated signal to the second selector controller 9. Further, it includes a noise removing circuit 12 for removing the noise involved in the output signal of the selector 8 to output the resulting noise-free signal on its output terminal 13.
In this conventional clock controller, there is fear that, if the clock switching signal is switched from its binary value “1” to “0” just before the clock #0 is switched from “1” to “0”, the first selector 4 changes its output to “0” at the instant the second selector 8 is switched, thus causing a whisker-like signal of a short pulse duration approximately corresponding to the period of a delay caused by the first delay circuit 6, that is, a hazard. However, the hazard caused at this time is of an extremely short duration and hence may be removed by the noise removing circuit 12. The clock switching signal is then supplied via the first delay circuit 6 to the first selector controller 5, thus rendering the output of the first selector 4 switched from the clock #0 to the clock #1, while the second selector 8 has selected the output of the signal holding circuit 7 and thence holds the signal of binary value “1”.
When the output of the first selector 4 is switched from the clock #0 to the clock #1, the counter 11 generates, after several clocks, a signal synchronized with the clock #1. Responsive to the synchronous signal thus output from the counter 11, a selector switching signal causes the second selector 8 to select, instead of the output of the signal holding circuit 7, the clock #1 output from the selector 4. Since the selector switching signal, received by the selector 8, is synchronized with the clock #1, no hazard is caused by the switching.
However, in the above-stated clock controller, the clock switching signal is delayed by the first and second delay circuits 6 and 10 in order to switch between the two clocks #0 and #1. It is therefore necessary to design the amount of delay with the relationship with respect to the frequencies of the clocks #0 and #1 taken into account. This necessitates complicated designing work in determining the amount of delay. In addition, the amount of delay is to be changed adaptively to changing the frequencies of the clocks #0 and #1.